    // Copyright (C) 1953-2023 NUDT
// Verilog module name - stored_forward_control
// Version: V3.2.0.20210722
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//          
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module stored_forward_control
#(
    parameter NUM_GMAC = 8,  
    parameter NUM_XGMAC = 0	
)
(
        i_clk,
        i_rst_n,

        i_pkt_rx_finish_empty   ,
        o_pkt_rx_finish_rd      ,
        i_pkt_rx_finish_rdata   ,
        /*
        i_pkt_rx_finish_empty_p0   ,
        o_pkt_rx_finish_rd_p0      ,
        i_pkt_rx_finish_rdata_p0   ,
                                   
        i_pkt_rx_finish_empty_p1   ,
        o_pkt_rx_finish_rd_p1      ,
        i_pkt_rx_finish_rdata_p1   ,
                                   
        i_pkt_rx_finish_empty_p2   ,
        o_pkt_rx_finish_rd_p2      ,
        i_pkt_rx_finish_rdata_p2   ,
                                   
        i_pkt_rx_finish_empty_p3   ,
        o_pkt_rx_finish_rd_p3      ,
        i_pkt_rx_finish_rdata_p3   ,
                                   
        i_pkt_rx_finish_empty_p4   ,
        o_pkt_rx_finish_rd_p4      ,
        i_pkt_rx_finish_rdata_p4   ,
                                   
        i_pkt_rx_finish_empty_p5   ,
        o_pkt_rx_finish_rd_p5      ,
        i_pkt_rx_finish_rdata_p5   ,
                                   
        i_pkt_rx_finish_empty_p6   ,
        o_pkt_rx_finish_rd_p6      ,
        i_pkt_rx_finish_rdata_p6   ,
                                   
        i_pkt_rx_finish_empty_p7   ,
        o_pkt_rx_finish_rd_p7      ,
        i_pkt_rx_finish_rdata_p7   ,
                                   
        i_pkt_rx_finish_empty_p8   ,
        o_pkt_rx_finish_rd_p8      ,
        i_pkt_rx_finish_rdata_p8   ,
                                   
        i_pkt_rx_finish_empty_p9   ,
        o_pkt_rx_finish_rd_p9      ,
        i_pkt_rx_finish_rdata_p9   ,
                                   
        i_pkt_rx_finish_empty_p10  ,
        o_pkt_rx_finish_rd_p10     ,
        i_pkt_rx_finish_rdata_p10  ,
                                   
        i_pkt_rx_finish_empty_p11  ,
        o_pkt_rx_finish_rd_p11     ,
        i_pkt_rx_finish_rdata_p11  ,
                                   
        i_pkt_rx_finish_empty_p12  ,
        o_pkt_rx_finish_rd_p12     ,
        i_pkt_rx_finish_rdata_p12  ,
                                   
        i_pkt_rx_finish_empty_p13  ,
        o_pkt_rx_finish_rd_p13     ,
        i_pkt_rx_finish_rdata_p13  ,
                                   
        i_pkt_rx_finish_empty_p14  ,
        o_pkt_rx_finish_rd_p14     ,
        i_pkt_rx_finish_rdata_p14  ,
                                   
        i_pkt_rx_finish_empty_p15  ,
        o_pkt_rx_finish_rd_p15     ,
        i_pkt_rx_finish_rdata_p15  ,
                                   
        i_pkt_rx_finish_empty_p16  ,
        o_pkt_rx_finish_rd_p16     ,
        i_pkt_rx_finish_rdata_p16  ,
                                   
        i_pkt_rx_finish_empty_p17  ,
        o_pkt_rx_finish_rd_p17     ,
        i_pkt_rx_finish_rdata_p17  ,
                                   
        i_pkt_rx_finish_empty_p18  ,
        o_pkt_rx_finish_rd_p18     ,
        i_pkt_rx_finish_rdata_p18  ,
                                   
        i_pkt_rx_finish_empty_p19  ,
        o_pkt_rx_finish_rd_p19     ,
        i_pkt_rx_finish_rdata_p19  ,
                                   
        i_pkt_rx_finish_empty_p20  ,
        o_pkt_rx_finish_rd_p20     ,
        i_pkt_rx_finish_rdata_p20  ,
                                   
        i_pkt_rx_finish_empty_p21  ,
        o_pkt_rx_finish_rd_p21     ,
        i_pkt_rx_finish_rdata_p21  ,
                                   
        i_pkt_rx_finish_empty_p22  ,
        o_pkt_rx_finish_rd_p22     ,
        i_pkt_rx_finish_rdata_p22  ,
                                   
        i_pkt_rx_finish_empty_p23  ,
        o_pkt_rx_finish_rd_p23     ,
        i_pkt_rx_finish_rdata_p23  ,
                                   
        i_pkt_rx_finish_empty_p24  ,
        o_pkt_rx_finish_rd_p24     ,
        i_pkt_rx_finish_rdata_p24  ,
                                   
        i_pkt_rx_finish_empty_p25  ,
        o_pkt_rx_finish_rd_p25     ,
        i_pkt_rx_finish_rdata_p25  ,
                                   
        i_pkt_rx_finish_empty_p26  ,
        o_pkt_rx_finish_rd_p26     ,
        i_pkt_rx_finish_rdata_p26  ,
                                   
        i_pkt_rx_finish_empty_p27  ,
        o_pkt_rx_finish_rd_p27     ,
        i_pkt_rx_finish_rdata_p27  ,
                                   
        i_pkt_rx_finish_empty_p28  ,
        o_pkt_rx_finish_rd_p28     ,
        i_pkt_rx_finish_rdata_p28  ,
                                   
        i_pkt_rx_finish_empty_p29  ,
        o_pkt_rx_finish_rd_p29     ,
        i_pkt_rx_finish_rdata_p29  ,
        
        i_pkt_rx_finish_empty_p30  ,
        o_pkt_rx_finish_rd_p30     ,
        i_pkt_rx_finish_rdata_p30  ,
        
        i_pkt_rx_finish_empty_p31  ,
        o_pkt_rx_finish_rd_p31     ,
        i_pkt_rx_finish_rdata_p31  ,
        
        i_pkt_rx_finish_empty_p32  ,
        o_pkt_rx_finish_rd_p32     ,
        i_pkt_rx_finish_rdata_p32  ,
        */
        //iv_desp     ,  
        //i_desp_wr   ,
        //i_cutthroughfwd ,
        //iv_pkt_inport   ,
        o_storedfwd_rd      , 
        iv_storedfwd_rdata  ,
        i_storedfwd_empty   ,
        
                    
        ov_desp       ,
        o_desp_wr          
);

// I/O
// clk & rst
input                  i_clk;                   //125Mhz
input                  i_rst_n;
//
input         [(NUM_XGMAC + NUM_GMAC + 1)  -1:0]         i_pkt_rx_finish_empty ;
output reg    [(NUM_XGMAC + NUM_GMAC + 1)  -1:0]         o_pkt_rx_finish_rd    ;
input         [(NUM_XGMAC + NUM_GMAC + 1)  -1:0]         i_pkt_rx_finish_rdata ;
/*
input                  i_pkt_rx_finish_empty_p0 ;
output reg             o_pkt_rx_finish_rd_p0    ;
input                  i_pkt_rx_finish_rdata_p0 ;
                                                
input                  i_pkt_rx_finish_empty_p1 ;
output reg             o_pkt_rx_finish_rd_p1    ;
input                  i_pkt_rx_finish_rdata_p1 ;
                                                
input                  i_pkt_rx_finish_empty_p2 ;
output reg             o_pkt_rx_finish_rd_p2    ;
input                  i_pkt_rx_finish_rdata_p2 ;
                         
input                  i_pkt_rx_finish_empty_p3 ;
output reg             o_pkt_rx_finish_rd_p3    ;
input                  i_pkt_rx_finish_rdata_p3 ;
                                                
input                  i_pkt_rx_finish_empty_p4 ;
output reg             o_pkt_rx_finish_rd_p4    ;
input                  i_pkt_rx_finish_rdata_p4 ;
                                                
input                  i_pkt_rx_finish_empty_p5 ;
output reg             o_pkt_rx_finish_rd_p5    ;
input                  i_pkt_rx_finish_rdata_p5 ;
                         
input                  i_pkt_rx_finish_empty_p6 ;
output reg             o_pkt_rx_finish_rd_p6    ;
input                  i_pkt_rx_finish_rdata_p6 ;
                                                
input                  i_pkt_rx_finish_empty_p7 ;
output reg             o_pkt_rx_finish_rd_p7    ;
input                  i_pkt_rx_finish_rdata_p7 ;
                                                
input                  i_pkt_rx_finish_empty_p8 ;
output reg             o_pkt_rx_finish_rd_p8    ;
input                  i_pkt_rx_finish_rdata_p8 ;
                         
input                  i_pkt_rx_finish_empty_p9 ; 
output reg             o_pkt_rx_finish_rd_p9    ;
input                  i_pkt_rx_finish_rdata_p9 ;
                                                
input                  i_pkt_rx_finish_empty_p10;
output reg             o_pkt_rx_finish_rd_p10   ;
input                  i_pkt_rx_finish_rdata_p10;
                                                
input                  i_pkt_rx_finish_empty_p11;
output reg             o_pkt_rx_finish_rd_p11   ;
input                  i_pkt_rx_finish_rdata_p11;
                         
input                  i_pkt_rx_finish_empty_p12;
output reg             o_pkt_rx_finish_rd_p12   ;
input                  i_pkt_rx_finish_rdata_p12;
                                                
input                  i_pkt_rx_finish_empty_p13;
output reg             o_pkt_rx_finish_rd_p13   ;
input                  i_pkt_rx_finish_rdata_p13;
                                                
input                  i_pkt_rx_finish_empty_p14;
output reg             o_pkt_rx_finish_rd_p14   ;
input                  i_pkt_rx_finish_rdata_p14;
                         
input                  i_pkt_rx_finish_empty_p15;
output reg             o_pkt_rx_finish_rd_p15   ;
input                  i_pkt_rx_finish_rdata_p15;
                                                
input                  i_pkt_rx_finish_empty_p16;
output reg             o_pkt_rx_finish_rd_p16   ;
input                  i_pkt_rx_finish_rdata_p16;
                                                
input                  i_pkt_rx_finish_empty_p17;
output reg             o_pkt_rx_finish_rd_p17   ;
input                  i_pkt_rx_finish_rdata_p17;
                         
input                  i_pkt_rx_finish_empty_p18;
output reg             o_pkt_rx_finish_rd_p18   ;
input                  i_pkt_rx_finish_rdata_p18;
                                                
input                  i_pkt_rx_finish_empty_p19;
output reg             o_pkt_rx_finish_rd_p19   ;
input                  i_pkt_rx_finish_rdata_p19;
                                                
input                  i_pkt_rx_finish_empty_p20;
output reg             o_pkt_rx_finish_rd_p20   ;
input                  i_pkt_rx_finish_rdata_p20;
                                                
input                  i_pkt_rx_finish_empty_p21;
output reg             o_pkt_rx_finish_rd_p21   ;
input                  i_pkt_rx_finish_rdata_p21;
                                                
input                  i_pkt_rx_finish_empty_p22;
output reg             o_pkt_rx_finish_rd_p22   ;
input                  i_pkt_rx_finish_rdata_p22;
                                                
input                  i_pkt_rx_finish_empty_p23;
output reg             o_pkt_rx_finish_rd_p23   ;
input                  i_pkt_rx_finish_rdata_p23;
                         
input                  i_pkt_rx_finish_empty_p24;
output reg             o_pkt_rx_finish_rd_p24   ;
input                  i_pkt_rx_finish_rdata_p24;
                                                
input                  i_pkt_rx_finish_empty_p25;
output reg             o_pkt_rx_finish_rd_p25   ;
input                  i_pkt_rx_finish_rdata_p25;
                                                
input                  i_pkt_rx_finish_empty_p26;
output reg             o_pkt_rx_finish_rd_p26   ;
input                  i_pkt_rx_finish_rdata_p26;
                                                
input                  i_pkt_rx_finish_empty_p27;
output reg             o_pkt_rx_finish_rd_p27   ;
input                  i_pkt_rx_finish_rdata_p27;
                                                
input                  i_pkt_rx_finish_empty_p28;
output reg             o_pkt_rx_finish_rd_p28   ;
input                  i_pkt_rx_finish_rdata_p28;
                                                
input                  i_pkt_rx_finish_empty_p29;
output reg             o_pkt_rx_finish_rd_p29   ;
input                  i_pkt_rx_finish_rdata_p29;

input                  i_pkt_rx_finish_empty_p30;
output reg             o_pkt_rx_finish_rd_p30   ;
input                  i_pkt_rx_finish_rdata_p30;
                       
input                  i_pkt_rx_finish_empty_p31;
output reg             o_pkt_rx_finish_rd_p31   ;
input                  i_pkt_rx_finish_rdata_p31;

input                  i_pkt_rx_finish_empty_p32; 
output reg             o_pkt_rx_finish_rd_p32   ;
input                  i_pkt_rx_finish_rdata_p32;
*/
// pkt_bufid and pkt_type and outport from lookup_table
//input      [87:0]      iv_desp;
//input                  i_desp_wr;
//input                  i_cutthroughfwd ;
//input      [5:0]       iv_pkt_inport   ;
output reg             o_storedfwd_rd     ;
input        [94:0]    iv_storedfwd_rdata ;//{i_cutthroughfwd,iv_pkt_inport,iv_desp}
input                  i_storedfwd_empty  ;
// pkt_bufid and pkt_type 
output reg [87:0]      ov_desp;
output reg             o_desp_wr;
//*****************************************//
reg        [1:0]       rv_sfc_state;
localparam  IDLE_S          = 2'd0,
            OUTPUT_S        = 2'd1,
			PORTID_ERROR_S  = 2'd2;
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        o_pkt_rx_finish_rd  <= 'b0;
		/*
		o_pkt_rx_finish_rd_p0  <= 1'b0;
        o_pkt_rx_finish_rd_p1  <= 1'b0;
        o_pkt_rx_finish_rd_p2  <= 1'b0;
        o_pkt_rx_finish_rd_p3  <= 1'b0;
        o_pkt_rx_finish_rd_p4  <= 1'b0;
        o_pkt_rx_finish_rd_p5  <= 1'b0;
        o_pkt_rx_finish_rd_p6  <= 1'b0;
        o_pkt_rx_finish_rd_p7  <= 1'b0;
        o_pkt_rx_finish_rd_p8  <= 1'b0;
        o_pkt_rx_finish_rd_p9  <= 1'b0;
        
        o_pkt_rx_finish_rd_p10  <= 1'b0;
        o_pkt_rx_finish_rd_p11  <= 1'b0;
        o_pkt_rx_finish_rd_p12  <= 1'b0;
        o_pkt_rx_finish_rd_p13  <= 1'b0;
        o_pkt_rx_finish_rd_p14  <= 1'b0;
        o_pkt_rx_finish_rd_p15  <= 1'b0;
        o_pkt_rx_finish_rd_p16  <= 1'b0;
        o_pkt_rx_finish_rd_p17  <= 1'b0;
        o_pkt_rx_finish_rd_p18  <= 1'b0;
        o_pkt_rx_finish_rd_p19  <= 1'b0;
        
        o_pkt_rx_finish_rd_p20  <= 1'b0;
        o_pkt_rx_finish_rd_p21  <= 1'b0;
        o_pkt_rx_finish_rd_p22  <= 1'b0;
        o_pkt_rx_finish_rd_p23  <= 1'b0;
        o_pkt_rx_finish_rd_p24  <= 1'b0;
        o_pkt_rx_finish_rd_p25  <= 1'b0;
        o_pkt_rx_finish_rd_p26  <= 1'b0;
        o_pkt_rx_finish_rd_p27  <= 1'b0;
        o_pkt_rx_finish_rd_p28  <= 1'b0;
        o_pkt_rx_finish_rd_p29  <= 1'b0;
        
        o_pkt_rx_finish_rd_p30  <= 1'b0;
        o_pkt_rx_finish_rd_p31  <= 1'b0;
        o_pkt_rx_finish_rd_p32  <= 1'b0;
        */
        o_storedfwd_rd          <= 1'b0;
        
        ov_desp                 <= 88'b0;
        o_desp_wr               <= 1'b0 ;
        
        rv_sfc_state            <= IDLE_S;
    end                              
    else begin
        case(rv_sfc_state)
            IDLE_S:begin
                ov_desp                 <= 88'b0;
                o_desp_wr               <= 1'b0 ;
                
                if(i_storedfwd_empty == 1'b0)begin 
                    if(iv_storedfwd_rdata[93:88] == (NUM_XGMAC + NUM_GMAC + 1)  -1)begin//hcp
						if(i_pkt_rx_finish_empty[(NUM_XGMAC + NUM_GMAC + 1)  -1] == 1'b0)begin
							o_pkt_rx_finish_rd[(NUM_XGMAC + NUM_GMAC + 1)  -1]  <= 1'b1;
							o_storedfwd_rd         <= 1'b1;
							rv_sfc_state           <= OUTPUT_S;                                 
						end
						else begin
							o_pkt_rx_finish_rd[(NUM_XGMAC + NUM_GMAC + 1)  -1]  <= 1'b0;
							o_storedfwd_rd         <= 1'b0;                             
						end
                    end
					else if(iv_storedfwd_rdata[93:88] <= (NUM_XGMAC + NUM_GMAC)  - 1)begin
						case(iv_storedfwd_rdata[93:88])
							6'd0 :begin
								if(i_pkt_rx_finish_empty[0] == 1'b0)begin
									o_pkt_rx_finish_rd[0]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                
								end
								else begin
									o_pkt_rx_finish_rd[0]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd1 :begin
								if(i_pkt_rx_finish_empty[1] == 1'b0)begin
									o_pkt_rx_finish_rd[1]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[1]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd2 :begin
								if(i_pkt_rx_finish_empty[2] == 1'b0)begin
									o_pkt_rx_finish_rd[2]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1; 
									rv_sfc_state           <= OUTPUT_S; 
								end
								else begin
									o_pkt_rx_finish_rd[2]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd3 :begin
								if(i_pkt_rx_finish_empty[3] == 1'b0)begin
									o_pkt_rx_finish_rd[3]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[3]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							/*
							6'd4 :begin
								if(i_pkt_rx_finish_empty[4] == 1'b0)begin
									o_pkt_rx_finish_rd[4]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[4]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd5 :begin
								if(i_pkt_rx_finish_empty[5] == 1'b0)begin
									o_pkt_rx_finish_rd[5]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[5]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd6 :begin
								if(i_pkt_rx_finish_empty[6] == 1'b0)begin
									o_pkt_rx_finish_rd[6]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1; 
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[6]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd7 :begin
								if(i_pkt_rx_finish_empty[7] == 1'b0)begin
									o_pkt_rx_finish_rd[7]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[7]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end  
							6'd8 :begin
								if(i_pkt_rx_finish_empty[8] == 1'b0)begin
									o_pkt_rx_finish_rd[8]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[8]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd9 :begin
								if(i_pkt_rx_finish_empty[9] == 1'b0)begin
									o_pkt_rx_finish_rd[9]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[9]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd10:begin
								if(i_pkt_rx_finish_empty[10] == 1'b0)begin
									o_pkt_rx_finish_rd[10]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[10]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd11:begin
								if(i_pkt_rx_finish_empty[11] == 1'b0)begin
									o_pkt_rx_finish_rd[11]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[11]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd12:begin
								if(i_pkt_rx_finish_empty[12] == 1'b0)begin
									o_pkt_rx_finish_rd[12]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[12]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd13:begin
								if(i_pkt_rx_finish_empty[13] == 1'b0)begin
									o_pkt_rx_finish_rd[13]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[13]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end 
							6'd14:begin
								if(i_pkt_rx_finish_empty[14] == 1'b0)begin
									o_pkt_rx_finish_rd[14]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[14]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd15:begin
								if(i_pkt_rx_finish_empty[15] == 1'b0)begin
									o_pkt_rx_finish_rd[15]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[15]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd16:begin
								if(i_pkt_rx_finish_empty[16] == 1'b0)begin
									o_pkt_rx_finish_rd[16]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[16]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd17:begin
								if(i_pkt_rx_finish_empty[17] == 1'b0)begin
									o_pkt_rx_finish_rd[17]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[17]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd18:begin
								if(i_pkt_rx_finish_empty[18] == 1'b0)begin
									o_pkt_rx_finish_rd[18]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[18]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd19:begin
								if(i_pkt_rx_finish_empty[19] == 1'b0)begin
									o_pkt_rx_finish_rd[19]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[19]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd20:begin
								if(i_pkt_rx_finish_empty[20] == 1'b0)begin
									o_pkt_rx_finish_rd[20]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[20]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd21:begin
								if(i_pkt_rx_finish_empty[21] == 1'b0)begin
									o_pkt_rx_finish_rd[21]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1; 
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[21]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd22:begin
								if(i_pkt_rx_finish_empty[22] == 1'b0)begin
									o_pkt_rx_finish_rd[22]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[22]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd23:begin
								if(i_pkt_rx_finish_empty[23] == 1'b0)begin
									o_pkt_rx_finish_rd[23]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[23]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd24:begin
								if(i_pkt_rx_finish_empty[24] == 1'b0)begin
									o_pkt_rx_finish_rd[24]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[24]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd25:begin
								if(i_pkt_rx_finish_empty[25] == 1'b0)begin
									o_pkt_rx_finish_rd[25]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[25]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd26:begin
								if(i_pkt_rx_finish_empty[26] == 1'b0)begin
									o_pkt_rx_finish_rd[26]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[26]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd27:begin
								if(i_pkt_rx_finish_empty[27] == 1'b0)begin
									o_pkt_rx_finish_rd[27]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[27]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd28:begin
								if(i_pkt_rx_finish_empty[28] == 1'b0)begin
									o_pkt_rx_finish_rd[28]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[28]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd29:begin
								if(i_pkt_rx_finish_empty[29] == 1'b0)begin
									o_pkt_rx_finish_rd[29]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[29]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd30:begin
								if(i_pkt_rx_finish_empty[30] == 1'b0)begin
									o_pkt_rx_finish_rd[30]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[30]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							6'd31:begin
								if(i_pkt_rx_finish_empty[31] == 1'b0)begin
									o_pkt_rx_finish_rd[31]  <= 1'b1;
									o_storedfwd_rd         <= 1'b1;
									rv_sfc_state           <= OUTPUT_S;                                 
								end
								else begin
									o_pkt_rx_finish_rd[31]  <= 1'b0;
									o_storedfwd_rd         <= 1'b0;                             
								end
							end
							*/
							default:begin
								o_pkt_rx_finish_rd  <= 'b0;
								o_storedfwd_rd      <= 1'b0; 
							end
						endcase                   
                    end
					else begin
					    o_pkt_rx_finish_rd     <= 'b0;
						o_storedfwd_rd         <= 1'b0;
						rv_sfc_state           <= PORTID_ERROR_S;
					end
				end
                else begin
				    o_pkt_rx_finish_rd  <= 'b0;
					/*
                    o_pkt_rx_finish_rd_p0  <= 1'b0;
                    o_pkt_rx_finish_rd_p1  <= 1'b0;
                    o_pkt_rx_finish_rd_p2  <= 1'b0;
                    o_pkt_rx_finish_rd_p3  <= 1'b0;
                    o_pkt_rx_finish_rd_p4  <= 1'b0;
                    o_pkt_rx_finish_rd_p5  <= 1'b0;
                    o_pkt_rx_finish_rd_p6  <= 1'b0;
                    o_pkt_rx_finish_rd_p7  <= 1'b0;
                    o_pkt_rx_finish_rd_p8  <= 1'b0;
                    o_pkt_rx_finish_rd_p9  <= 1'b0;
                    
                    o_pkt_rx_finish_rd_p10  <= 1'b0;
                    o_pkt_rx_finish_rd_p11  <= 1'b0;
                    o_pkt_rx_finish_rd_p12  <= 1'b0;
                    o_pkt_rx_finish_rd_p13  <= 1'b0;
                    o_pkt_rx_finish_rd_p14  <= 1'b0;
                    o_pkt_rx_finish_rd_p15  <= 1'b0;
                    o_pkt_rx_finish_rd_p16  <= 1'b0;
                    o_pkt_rx_finish_rd_p17  <= 1'b0;
                    o_pkt_rx_finish_rd_p18  <= 1'b0;
                    o_pkt_rx_finish_rd_p19  <= 1'b0;
                    
                    o_pkt_rx_finish_rd_p20  <= 1'b0;
                    o_pkt_rx_finish_rd_p21  <= 1'b0;
                    o_pkt_rx_finish_rd_p22  <= 1'b0;
                    o_pkt_rx_finish_rd_p23  <= 1'b0;
                    o_pkt_rx_finish_rd_p24  <= 1'b0;
                    o_pkt_rx_finish_rd_p25  <= 1'b0;
                    o_pkt_rx_finish_rd_p26  <= 1'b0;
                    o_pkt_rx_finish_rd_p27  <= 1'b0;
                    o_pkt_rx_finish_rd_p28  <= 1'b0;
                    o_pkt_rx_finish_rd_p29  <= 1'b0;
                    
                    o_pkt_rx_finish_rd_p30  <= 1'b0;
                    o_pkt_rx_finish_rd_p31  <= 1'b0;
                    o_pkt_rx_finish_rd_p32  <= 1'b0;
                    */
                    o_storedfwd_rd          <= 1'b0;
                    
                    rv_sfc_state            <= IDLE_S;
                end            
            end
            OUTPUT_S:begin
                rv_sfc_state            <= IDLE_S;
                if(iv_storedfwd_rdata[94])begin//cutthroughfwd
                    ov_desp                 <= 88'b0;
                    o_desp_wr               <= 1'b0 ;                
                end
                else begin//stored
                    ov_desp                 <= iv_storedfwd_rdata[87:0];
                    o_desp_wr               <= 1'b1 ;                 
                end
                o_pkt_rx_finish_rd  <= 'b0;
				/*
                o_pkt_rx_finish_rd_p0  <= 1'b0;
                o_pkt_rx_finish_rd_p1  <= 1'b0;
                o_pkt_rx_finish_rd_p2  <= 1'b0;
                o_pkt_rx_finish_rd_p3  <= 1'b0;
                o_pkt_rx_finish_rd_p4  <= 1'b0;
                o_pkt_rx_finish_rd_p5  <= 1'b0;
                o_pkt_rx_finish_rd_p6  <= 1'b0;
                o_pkt_rx_finish_rd_p7  <= 1'b0;
                o_pkt_rx_finish_rd_p8  <= 1'b0;
                o_pkt_rx_finish_rd_p9  <= 1'b0;
                
                o_pkt_rx_finish_rd_p10  <= 1'b0;
                o_pkt_rx_finish_rd_p11  <= 1'b0;
                o_pkt_rx_finish_rd_p12  <= 1'b0;
                o_pkt_rx_finish_rd_p13  <= 1'b0;
                o_pkt_rx_finish_rd_p14  <= 1'b0;
                o_pkt_rx_finish_rd_p15  <= 1'b0;
                o_pkt_rx_finish_rd_p16  <= 1'b0;
                o_pkt_rx_finish_rd_p17  <= 1'b0;
                o_pkt_rx_finish_rd_p18  <= 1'b0;
                o_pkt_rx_finish_rd_p19  <= 1'b0;
                
                o_pkt_rx_finish_rd_p20  <= 1'b0;
                o_pkt_rx_finish_rd_p21  <= 1'b0;
                o_pkt_rx_finish_rd_p22  <= 1'b0;
                o_pkt_rx_finish_rd_p23  <= 1'b0;
                o_pkt_rx_finish_rd_p24  <= 1'b0;
                o_pkt_rx_finish_rd_p25  <= 1'b0;
                o_pkt_rx_finish_rd_p26  <= 1'b0;
                o_pkt_rx_finish_rd_p27  <= 1'b0;
                o_pkt_rx_finish_rd_p28  <= 1'b0;
                o_pkt_rx_finish_rd_p29  <= 1'b0;
                
                o_pkt_rx_finish_rd_p30  <= 1'b0;
                o_pkt_rx_finish_rd_p31  <= 1'b0;
                o_pkt_rx_finish_rd_p32  <= 1'b0;
                */
                o_storedfwd_rd          <= 1'b0;            
            end
            PORTID_ERROR_S:begin            
			    o_pkt_rx_finish_rd     <= 'b0;
			    o_storedfwd_rd         <= 1'b0;
			    rv_sfc_state           <= PORTID_ERROR_S;
			end
			default:begin
                ov_desp                 <= 88'b0;
                o_desp_wr               <= 1'b0 ;                  
                
                rv_sfc_state            <= IDLE_S;
            end
        endcase
    end
end                  

endmodule
